1. Technical Field
The present invention relates to phase locked loops and, more particularly, to a prediction-based control scheme for a digital control path of a fractional-N phase locked loop.
2. Description of the Related Art
Phase locked loops (PLLs) are components in many systems, e.g., microprocessors, millimeter-wave radios, and serial links. Digital PLLs may be used wherever reducing the power and area requirements of the PLL is important. One type of PLL that has been difficult to transition to digital is the fractional-N PLL. A fractional-N PLL is a PLL which generates an output frequency having a non-integer or fractional ratio to the input reference frequency. A fractional-N PLL typically achieves this by modulating the division ration of the PLL's feedback divider in integer steps, so as to achieve an average fractional (non-integer) net division ration.
Conventional analog fractional-N PLLs use linear charge pumps and analog loop filters. The large capacitor in the loop filter is relatively expensive. Furthermore, conventional bang-bang digital PLLs do not work well in fractional-N mode. As a result of the non-linearity of the bang-bang phase detector, the output phase noise is corrupted. Very fast reference rates are needed for such digital PLLs to achieve even moderate performance.